1. Field of the Invention
The invention relates to a booster power management integrated chip, more particularly to a booster power management integrated circuit chip that includes an electrostatic discharge (ESD) protection mechanism.
2. Description of the Related Art
Static electricity is always present in our surrounding environment. In particular, when an object that carries static electricity comes into contact with a terminal of an integrated circuit chip, an instantaneous high voltage discharge can have an adverse affect on electric circuits connected to that terminal. This phenomenon, which is known as electrostatic discharge (abbreviated as ESD), is one of the most common causes of failure in electronic systems.
As shown in FIG. 1, a conventional ESD protection circuit 1 is embedded in an integrated circuit chip 2 having a pair of pads 20, 21. The ESD protection circuit 1 is coupled between the pads 20, 21 of the integrated circuit chip 2 so as to protect an electric circuit that is also coupled between the pads 20, 21 from possible damage due to ESD. The conventional ESD protection circuit 1 includes an ESD component 11 (such as a NMOS transistor), a voltage drop circuit 12 coupled between the pad 20 and a gate of the ESD component 11, and a resistor 13 coupled between the gate of the ESD component 11 and the pad 21.
The voltage drop circuit 12 includes a plurality of MOS transistors 121 that are connected in series. Under normal operating conditions, since the output voltage between the pads 20, 21 is lower than a trigger voltage level, the ESD component 11 is unable to conduct. The trigger voltage level is the sum of the lowest drive voltage for the voltage drop circuit 12 and the lowest conduction threshold voltage of the ESD component 11.
On the other hand, when ESD is present between the pads 20, 21, if an instantaneous voltage attributed to the ESD is larger than the trigger voltage level, the ESD component 11 will conduct such that electric current will be able to flow therethrough. As a result, a large portion of the high electric current attributed to the ESD can be diverted to protect the electric circuit 3 from damage.
In general, the ESD component 11 (in this instance, a NMOS transistor) has a channel width of only about 400 μm such that the channel resistance thereof is about 20 ohms. With reference to FIG. 2, the instantaneous high electric current attributed to the ESD will generate a high voltage across the channel resistance that can cause a parasitic bipolar junction transistor (abbreviated as BJT) 110 of the ESD component 11 to conduct. As a result, both the BJT 110 and the channel of the ESD component 11 conduct current and share the load of the ESD current. However, when the BJT 110 conducts, it has a non-uniform characteristic in that higher temperatures can cause higher electric current concentration. Hence, a large portion of the ESD current will concentrate at the BJT 110, which is the first to conduct, such that the ESD component 11 is prone to burn out due to localized overheating as a result of a high electric current density through the BJT 110.
In view of the above, it has been proposed heretofore to add a series resistance 14 (see FIG. 3) in the ESD component 11 to eliminate the temperature effect of the BJT 110 and to achieve an effect of greater current dispersion for higher temperatures, thereby protecting the ESD component 11 from damage due to localized overheating. Nevertheless, this results in an increased component area for the ESD component 11.
Referring to FIG. 4, a conventional booster (or boost converter) 4 is used to boost an input voltage (Vin) provided by a power management integrated circuit chip 5 to a higher level for subsequent output. The power management integrated circuit chip 5 includes a MOS transistor switch 41 (in this instance, a NMOS transistor) coupled between first and second output pads 51, 52. Aside from the integrated circuit chip 5, the booster 4 further includes an inductor 42 for coupling the input voltage (Vin) to the first output pad 51, a diode 44 connected to the first output pad 51, and a capacitor 43 coupled between the diode 44 and the second output pad 52.
The MOS transistor switch 41 has a gate coupled to a control circuit 45. When the MOS transistor switch 41 is turned on in response to control activity of the control circuit 45, the inductor 42 is charged by the input voltage (Vin). When the MOS transistor switch 41 is turned off in response to control activity of the control circuit 45, the inductor 42 charges the capacitor 43 through the diode 44. As a result, electric energy is transferred to the capacitor 43 for storage such that the output voltage (Vout) from the capacitor 43 will be higher than the input voltage (Vin), thereby achieving a voltage boosting effect.
It is noted that the conventional booster 4 does not incorporate an ESD protection mechanism in view of the following: In view of circuit size considerations, it is not possible to add a sufficiently large series resistance in the MOS transistor switch 41 so as to eliminate the temperature effect of a parasitic BJT. Moreover, the conduction voltage of the parasitic BJT is not larger than that of the parasitic BJT of the ESD component 11 in FIG. 1. If the conventional ESD protection circuit 1 of FIG. 1 is to be added into the booster 4, the resulting circuit will be that shown in FIG. 5, in which a resistor 46 must be coupled between a drain of the MOS transistor switch 41 and the ESD protection circuit 1 such that the ESD voltage will not directly harm the MOS transistor switch 41. However, the resistor 46 will affect the output voltage of the booster 4, thereby adversely affecting operating efficiency of the booster 4.
Furthermore, since the channel of the MOS transistor switch 41 in the conventional booster 4 would not open during the occurrence of ESD, only the parasitic BJT is available to eliminate static electricity. However, in view of circuit size considerations, it is not possible to add a sufficiently large series resistance for the parasitic BJT. As a result, the MOS transistor switch 41 is prone to burn out due to the heat concentration effect of the electric currents generated during the occurrence of ESD.